CDR circuits (or systems) are generally used to sample an incoming data signal, extract the clock from the incoming data signal, and retime the sampled data. A phase-locked loop (PLL)-based CDR circuit is a conventional type of CDR circuit. By way of example, in a conventional PLL based CDR, a phase detector compares the phase between input data bits from a serial input data stream and a clock signal from a voltage-controlled oscillator (VCO). In response to the phase difference between the input data and the clock, the phase detector generates signals UP and DN. A charge pump drives a current to or from a loop filter according to the UP and DN signals. The loop filter generates a control voltage VCTRL for the VCO based on the UP and DN signals. The loop acts as a feedback control system that tracks the phase of input data stream with the phase of the clock that the loop generates. The dynamics of the loop are generally determined by the open loop gain and the location of open loop zeroes and poles (predominantly in the loop filter).
When multiple phases of a periodic signal are needed, such as with a clock signal used for clock and data recovery (CDR), a challenge is to accurately generate these multiple phases. Conventionally, delay-locked loops (DLL) and phase interpolators (PI) have been used to generate the needed phases in conjunction with conventional voltage-controlled oscillators. One problem with these devices is the accuracy obtained when generating phases having intermediate degree increments.
Various applications such as DLLs, 90 degree shifters, phase interpolators, and generators of adjustable clock phases require a high-speed phase detector whose output is zero for a 90 degree or other non-zero phase offset between inputs. The speed of conventional phase detectors, such as a phase and frequency detector (PFD) or an Alexander Detector, are limited by the speed of the flip-flops which are their integral parts. In addition, these conventional phase detectors are designed to output zero for nominal zero input phase offset, and are typically asymmetric in that the output of such phase detectors has a built-in phase offset between its inputs. The phase offset output from the phase detector typically cannot be compensated.